VHDL PROGRAM 3:8 DE-MULTIPLEXER
WITHOUT CASE STATEMENT
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| VHDL |
Object: Write a program (WAP) in VHDL Design, simulate & synthesis of 3:8 De-multiplexer without case statement and finally implement it on FPGA board.
Software required: Xilinx ISE 9.2i, PC, Power supply.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEC_38 is
Port ( D : in STD_LOGIC_VECTOR(2 DOWNTO 0); E: IN STD_LOGIC;
Y : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end DEC_38;
architecture Behavioral of DEC_38 is begin
process(D,E) begin
IF(E='1') THEN
case D is
when "111" => y<="00000001"; when "110" => y<="00000010"; when "101" => y<="00000100"; when "100" => y<="00001000"; when "011" => y<="00010000"; when "010" => y<="00100000";
when "001" => y<="01000000"; when OTHERS => y<="10000000"; end case; ELSE Y<="00000000"; END IF;
end process; end Behavioral;
Block diagram
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| Block Diagram |
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| Logical Diagram |
Technical
view:
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| Technical view |
E
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D2
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D1
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D0
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Y7
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Y6
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Y5
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Y4
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Y3
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Y2
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Y1
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Y0
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1
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0
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0
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0
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0
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0
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0
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0
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0
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0
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0
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1
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1
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0
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0
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1
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0
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0
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0
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0
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0
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0
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1
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0
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1
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0
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1
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0
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0
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0
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0
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0
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0
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1
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0
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0
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1
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0
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1
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1
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0
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0
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0
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0
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1
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0
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0
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0
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1
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1
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0
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0
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0
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0
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0
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1
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0
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0
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0
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0
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1
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1
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0
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1
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0
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0
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1
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0
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0
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0
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0
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0
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1
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1
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1
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0
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0
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1
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0
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0
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0
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0
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0
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0
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1
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1
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1
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1
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1
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0
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0
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0
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0
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0
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0
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0
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Waveforms:
Result: I
have simulated 3:8 Demultiplexer without case
statement and verified it.