VHDL code for 2 to 4 De-multiplexer Program

VDDL

Object: Write a program (WAP) in VHDL Design, simulate & synthesis of 2:4 De-multiplexer using when statement and finally implement it on FPGA board.

Software required: Xilinx ISE 9.2i, PC, Power supply.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all; entity DEC_2_4 is
Port (D:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Y : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end DEC_2_4;
architecture Behavioral of DEC_2_4 is begin
Y<="0001" WHEN D="00" ELSE "0010" WHEN D="01" ELSE "0100" WHEN D="10" ELSE "1000" WHEN D="11";
end Behavioral;


Block diagram

Block Diagram
Logical Diagram



Logical Diagram

Technical view:

Technical View

Truth table

D1
D0
Y3
Y2
Y1
Y0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
1
1
0
0
0


Waveforms:


Waveform

Result: I have simulated 2:4 de-mux using when statement &                       verified it.