VHDL code for 8 to 3 ENCODER Program

VHDL

Object: Write a program (WAP) in VHDL Design, simulate & synthesis of 8:3 ENCODER and finally implement it on FPGA board.


Software required: Xilinx ISE 9.2i, PC, Power supply.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encoder8 is
    Port ( S : in  STD_LOGIC;
           T : in  STD_LOGIC;
           U : in  STD_LOGIC;
           V : in  STD_LOGIC;
           W : in  STD_LOGIC;
           X : in  STD_LOGIC;
           Y : in  STD_LOGIC;
           Z : in  STD_LOGIC;
           OUT0 : out  STD_LOGIC;
           OUT1 : out  STD_LOGIC;
           OUT2 : out  STD_LOGIC);
end encoder8;

architecture Behavioral of encoder8 is

begin
            OUT0 <= T OR V OR X OR Z;
            OUT1 <= U OR V OR Y OR Z;
            OUT2 <= W OR X OR Y OR Z;

end Behavioral;



Block diagram
 
Block Diagram

Logical Diagram
  
Logical Diagram


Technical view:

Technical View

Waveforms:



 ResultI have simulated 8:3 ENCODER  & verified it.